Semiconductor circuit for arithmetic operation and method of arithmetic operation

ABSTRACT

There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders  1-3 ) for outputting carry data representing this carry, and delay means (memory  4 ) for delaying the computation result from the computation circuit by one computation time unit, are provided.

TECHNICAL FIELD

This invention relates to a semiconductor circuit for arithmeticprocessing and an arithmetic processing method, and particularly to asemiconductor circuit for arithmetic processing and an arithmeticprocessing method using information processing and device control.

BACKGROUND ART

In the field of information processing etc., semiconductor circuits areresponsible for numerical computation and logical computation.Accordingly, semiconductor circuits are extremely important in the fieldof information processing etc., and various circuits are currently beingdesigned.

In semiconductor circuits, first of all information is divided intoanalog information and digital information, but it is necessary toperform arithmetic processing after converting all information todigital information in order to carry out computation maintaining highreliability. For this reason, it is a general rule in the presentinvention that analog information is converted to multi-valueinformation or a digital signal and then arithmetic processing iscarried out.

Information that has been converted to digital becomes numericalinformation, and depending on the range of the numerical informationobtained data having a bit width of 8 bits, 16 bits, 32 bits, orcurrently 64 bits or 128 bits, is used. Circuit types for processingthis type of multi-bit information are generally classified into bitparallel circuits and bit serial circuits.

Bit parallel processing involves providing a calculating circuit for allbits, inputting data sequentially in bit units from the lower order bit,and performing calculation processing. It is no exaggeration to say thatas well as microprocessors, almost all current processors adopt thismethod.

Bit serial processing is a method of computational processing where datais input in bit units sequentially from lower order bits everycomputation time unit (normally a clock). With this method it ispossible to design computation circuits for 1 bit, and has the advantagethat surface area is small. However, since this method to carries outprocessing from a lower order digit, there is the disadvantage that ittakes am extremely long time to acquire data of the most significantdigit.

If it could be said that either the high order digit or the low orderhas more important information, then normally the high order has themost important information. That is why the highest order digit iscalled the Most Significant Digit. However, carrying out theconventional bit serial processing from the low order digit causes a“carry signal” problem in addition computation etc.

In a carry signal and addition result generated by addition computation,first of all the digit (decimal number) as the first placed number isdifferent, and it is not possible to handle in the same level.

Also, in the worst case there is a possibility of a carry signalgenerated from the least significant digit being propagated to the mostsignificant digit, and it is necessary to determine a solution and acarry signal from the least significant digit. Computational processingfrom an upper digit is impossible in the present invention withoutsolving this carry propagation problem.

Naturally, with computation that is not equivalent to a carry signal,such as a simple size judgement circuit, for example, there arearithmetic processing semiconductor circuits including comparativejudgment from an upper digit. However, there are no inventions forarithmetic processing from an upper order digit including arithmeticprocessing so as to include a carry signal.

The object of the present invention is to provide an semiconductorcircuit for arithmetic processing and an arithmetic processing methodthat can carry out arithmetic processing from an upper digitsequentially in bit serial format, with priority given to an upper orderdigit containing more important information.

In order to achieve the above described object, a first aspect of thepresent invention solves the problem of carry signal overflow inaddition computation, a second aspect of the present invention solvesthe problem of carry propagation, a third aspect of the presentinvention solves the problem of computation speed for bit serial format,and a fourth aspect of the present invention makes it possible toperform complicated computation and processing, other thanmultiplication, from an upper digit.

DISCLOSURE OF THE INVENTION

Computation that is a subject of the present invention is computationfrom an upper digit on data bit serially input every time step(computation time units), and resolves a generated carry signal usingvarious means, and realizes applications uses as a result.

A semiconductor circuit for arithmetic processing of the presentinvention is a semiconductor circuit receiving as input at least onenumerical data item comprised of a plurality of digits, inputsequentially one digit per computing time unit from an upper digit ofthe numerical data, and is provided with a computing unit for computingof the input data. The computing unit comprises a computing circuit forcomputing input digit data within a computing time unit, and outputtinga computation result representing a result obtained by the computationto generate a carry using the computation and outputting carry datarepresenting this carry, and delay means for delaying the computationalresult from the computing circuit by only a single computing time unit.Using this delay, the first aspect of the present invention resolves theproblem of carry signal overflow without the need for specializedhandling of the carry signal as a carry signal.

The problem of carry propagation in the semiconductor circuit forarithmetic processing of the present invention can be solved with thesecond aspect of the present invention by any of three methods.

First of all, using a method of representing output data using aredundant number system. Secondly, here is a method comprising firstdecision means for deciding whether or not the carry data output to anupper digit by computation of a particular digit is changed using carrydata generated by computation for a lower digit than that digit, outputmeans for indicating the fact that there is no change to carry data toan upper order side, when tho decision result from the first decisionmeans indicates that there is no dependency on carry data output fromthe lower order digit, input means for holding lower order side carrydata, when the decision result from the first decision means indicatesthat there is dependency on carry data output from the lower orderdigit, and changing means for changing the computational result inresponse to lower order digit carry data from the lower order side.Thirdly, there is a method comprising computing means for sequentiallycarrying out computation every computing time unit from an upper digitside and computing a maximum value and a minimum value for computationalresults acquired at the lower digit than an input digit, and comparisonmeans for comparing at least one of the maximum value and the minimumvalue computed by the computing means with data of another digit.

The third aspect of the present invention is a semiconductor circuit forarithmetic processing provided with decision means for comparing anddeciding, every computing time unit from an upper digit, computationalresults output sequentially every computing time unit from the upperdigit, and when the authenticity of the decision result of the decisionmeans has been confirmed arithmetic processing including comparison anddecision for remaining lower order digits is omitted.

A fourth aspect of the semiconductor circuit for arithmetic, processingof the present invention receives one of two data items as amultiplicand and the other as a multiplier, and sequentially inputs themultiplier every computing time unit from the upper order digit, andoutputs the result of multiplying the two data items sequentially everycomputing time unit from an upper order digit, and comprises storagemeans for storing the multiplier while shifting it every one computingtime unit, first computing means for respectively computing partialproducts of the multiplier from the storage means and the multiplicand,and generating and outputting all partial products of the same digit forthe multiplicand sequentially from the most significant digit everycomputing time unit, and second computing means for adding all partialproducts representing the same digit from the first computing means tooutput one multiplication result from an upper order digit.

An arithmetic processing method of the present invention involvesreceiving input of at least one numerical data item comprised of aplurality of digits, input sequentially from an upper order digit of thenumerical data, and includes a first process of computing data of aninput digit in computing time units and outputting a computation resultobtained by computation, a second process of generating a carry as aresult of the computation of the first process and outputting carry datarepresenting this carry, and a third process of delaying thecomputational result by only a single computing time unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a semiconductor circuit for arithmeticprocessing of a first embodiment of the present invention.

FIG. 2 is an explanatory drawing describing the data input timing for anadder 2 of the first embodiment.

FIG. 3 is an explanatory drawing describing elements of the adder of thefirst embodiment.

FIG. 4 is a circuit diagram of an initial stage adder used in a thirdembodiment.

FIG. 5 is a circuit diagram of a next stage adder used in the thirdembodiment.

FIG. 6 is a block diagram of a semiconductor circuit for arithmeticprocessing of a fourth embodiment of the present invention.

FIG. 7 is a block diagram of a semiconductor circuit for arithmeticprocessing of a fifth embodiment of the present invention.

FIG. 8 is a block diagram of a semiconductor circuit for arithmeticprocessing of a sixth embodiment of the present invention.

FIG. 9 is a block diagram of a semiconductor circuit for arithmeticprocessing of a seventh embodiment of the present invention.

FIG. 10 is an explanatory drawing for describing how to search a rangeaccording to the seventh embodiment.

FIG. 11 is a block diagram of a semiconductor circuit for arithmeticprocessing of a eighth embodiment of the present invention.

FIG. 12 is a block diagram of a semiconductor circuit for arithmeticprocessing of a ninth embodiment of the present invention.

FIG. 13 is an explanatory drawing describing an A/D conversion operationof the ninth embodiment.

FIG. 14 is an explanatory drawing for describing a tenth embodiment ofthe present invention.

FIG. 15 a block diagram of a semiconductor circuit for arithmeticprocessing of an eleventh embodiment of the present invention.

FIG. 16 is an explanatory drawing for describing multiplication in theeleventh embodiment.

FIG. 17 a block diagram of a semiconductor circuit for arithmeticprocessing of an twelfth embodiment of the present invention.

FIG. 18 a block diagram of a semiconductor circuit for arithmeticprocessing of an thirteenth embodiment of the present invention.

FIG. 19 is an explanatory drawing for describing multiplication in thethirteenth embodiment.

FIG. 20 is an explanatory drawing for describing the principal of afourteenth embodiment of the present invention.

FIG. 21 a block diagram of a semiconductor circuit for arithmeticprocessing of the fourteenth embodiment.

FIG. 22 is a block diagram showing one example of a carry controlcircuit of the fourteenth embodiment.

FIG. 23 a block diagram of a semiconductor circuit for arithmeticprocessing of a fifteenth embodiment of the present invention.

DESCRIPTION OF SYMBOLS

1-3, 21, 26A, 26B, 56A, 56E, 56B-56D, 61 adder

4, 5, 8, 9, 14, 33, 41A, 41B, 602, 68 ₁-68 _(n) memory

101A-101C, 201A, 201B neuron MOS inverter

101D-101F, 201C, 201D inverter

6, 7 difference circuit

10 minimum value circuit

11 difference circuit

12 forward rotation circuit

13 state storage circuit

22 delay circuit

23, 27, 28 comparator

24 storage circuit

29 AND gate

31, 32 general purpose circuit

36 A/D converter

37 calculation circuit

42A, 42B data bus

43 semiconductor circuit for arithmetic processing

45A-45H shift register

46A-46H partial product generating circuit

47A-47D, 48A, 48B, 49 redundant adder

51A-51H, 52A-52D, 53A, 53B, 54 general purpose calculator

61 m-63 m delay element

56 adding line section

57 redundant adder

62, 63 carry control circuit

601 state control circuit

603 output circuit

66 redundant conversion circuit

67 ₁-67 _(n) carry processing circuit

a1-a9, a11, a12, a21, a22, a26, a27, a31-a33, b31, a51 ₁-a51 ₁₆, a61,a36 analog signal

a55 multiplicand

a56 multiplier

a62, a66 data

b6, b7, b12 difference signal

b21, b56, c56, b62, c62, d62, s1, s2 addition signal

b26 maximum value signal

b27 minimum value signal

b36 digital signal

b51, c52, d53 control instruction

b63, c63, d63 state signal

b67, b68, c67 conversion result

c1-c4, b11, c26, c27, b55, c55, b61, c61, d61, b66,

c6, c21, d11, d31, e55, d66 control clock

c11 absolute value signal

c66 carry signal

d1, d2, b32, c31, c32, b37, e22, a601 control signal

d21, d22 average value signal

s3, s4 intermediate sum component

A37 half range

A38 quarter range

A39 eighth range

A45 range

A55, A56 line

B1, A36 full range

B2-B5 range

T1-T5, T71-T74 timing

Embodiments

Embodiments of the present invention will now be described withreference to the drawings.

In the following description, “digit” has the following meaning.Specifically, when data is represented by a numerical value, a “digit”refers to a unit when this data is subjected to arithmetic processing,and in the decimal system is called a “position”. “computation” is notlimited to numerical computation, and also includes logical computation.Specifically, “upper order digit” represents a digit one digit largerthan a digit currently being processed, while a “lower order digit”represents a digit one digit smaller. “upper order digit side” refers toupper order digits of a plurality of digits continuous from a digitcurrently being processed, while “lower order digit side” refers tolower order digits of a plurality of digits continuous from a digitcurrently being processed.

Also, a “redundant number system” refers to a number system that permitseach digit of an N base system to assume at least N+1 values.

[First Embodiment]

A first embodiment is an application of the present invention to asemiconductor circuit for arithmetic processing for adding data. In thefirst embodiment, a binary SD (signed digit) number system is used as aredundant base n number system. The binary SD number system is oneredundant number system, and permits numbers of redundant value called“−1”, that were not available originally, for binary numbers comprisedof combinations of “0's” and “1's”. An example of an arithmetic ruleusing this binary SD number system is shown in table 1. In the followingdescription, for example, when data “010” is represented in the binarySD number system this data is shown as “010”_(SD), while when data “010”is being represented in the binary system the data is shown as“010”_(S). Also, data “2” being represented in the decimal system isshown as “2”_(D).

TABLE 1 A −1 0 1 B −1 −1 · 0  −1 · 1  0 · 0  0 · −1 0 −1 · 1  0 · 0 0 ·1  0 · −1  1 · −1 1 0 · 0 0 · 1 1 · 0  1 · −1

In table 1, the two characters before the symbol “.” represent the“carry”, while the single character after the symbol represents the“sum”. Table 1 is an arithmetic rule representing addition of value Aand value B. The result of adding the two values is represented by a“sum” value and a “carry” value. At this time, “sum” represents theadded value of value A and value B, and “carry” represents carry data.In the following, “carry” is called a carry signal and “sum” is called asum signal. It is possible for “1” to “−1” to be generated as the“carry”, and there are also combinations of a number of representationtechniques.

With this binary SD number system, for example, when calculation isperformed from the least significant digit in the case of addition thereis a technique of only propagating a carry signal generated in theaddition to an upper order 2 digits. Specifically, the carry signal onlyhas an effect as far as the addition result of the two upper orderdigits from the digit where that signal was generated. This is acharacteristic feature of the binary SD number system.

A semiconductor circuit for arithmetic processing using this binary SDnumber system is shown in FIG. 1. The semiconductor circuit forarithmetic processing of FIG. 1 comprises adders 1-3 and memories 4 and5.

The adder 1 is an initial stage, that is, an input side, computingcircuit inside the semiconductor circuit for arithmetic processing. Dataa1 and data a2 are input to the adder 1. The data a1 represents onedigit within a number, and the data a2 represents one digit withinanother number. The numbers are represented in the binary SD numbersystem, and so data a1 and data a2 are both one of “−1”, “0” or “1”. Thedigits represented by data a1 and data a2 are sequentially input to theadder 1 from the highest order within the numbers.

The adder 1 reads in the data a1 an a1 on the rising edge of a pulseincluded in a control signal, and adding of the data a1 and the data a2is performed before the rising edge of the next control signal. When thedata a1 and the data a2 are added, the adder 1 follows the arithmeticrule shown in the following table 2.

TABLE 2 input internal sum (A + B) value carry signal sum signal (−1) +(−1) −2 −1 0 (−1) + 0 −1 −1 1 0 + (−1) 0 + 0 (−1) +1 0 0 0 1 + (−1) 0 +1 1 0 1 1 + 0 1 + 1 2 1 0

Values of each digit represented by data a1 and data a2 are in the range“−1”-“1”, which means that an addition result inside internal to theadder 1 is in the range “−2” to “2”. When the addition result is “−2”the adder 1 makes the value of a carry signal c1 of the binary SD numbersystem “−1”, and makes the sum signal s1 “0”. The adder 1 outputs thecarry signal c1 having a value “−1” to the adder 2 and outputs the sumsignal having the value “0” to the memory 4.

When the addition result inside the adder 1 is “2”, the adder 1 makesthe value of the carry signal c1 “1”, and makes the value of the sumsignal s1 “0”. When the addition result inside the adder 1 is “0”, theadder 1 makes the values of the carry signal c1 “1” and the sum signals1 “0”.

When the addition result inside the adder 1 is “−1”, the adder 1 makesthe value of the carry signal c1 “−1”, and makes the value of the sumsignal s1 “1”. When the addition result inside the adder 1 is “1”, theadder 1 makes the value of the carry signal c1 “0”, and makes the valueof the sum signal s1 “1”. That is, when the addition result internal tothe adder 1 has a value of “−1” or “1”, the adder 1 outputs “1” as thevalue of the sum signal s1.

The memory 4 stores the sum signal s1 from the adder 1 on the risingedge of control signal d1. A period of time from the rising edge of thecontrol signal d1 to next the rising edge of the control signal d1constitutes a computation time unit (step). That is, the memory 4 delaysthe value of the sum signal s1 by a single computation time unit ofcontrol signal d1 (from a pulse of the control signal to the nextpulse), then outputs the sum signal s1 to the adder 2. In the firstembodiment a D-type flip-flop for reading data on the rising edge of apulse is used as the memory 4. It is also possible to use an RSflip-flop or a JK flip-flop instead of the D-type flip-flop.

The adder 2 is an intermediate stage computing circuit inside thesemiconductor circuit for arithmetic processing. The carry signal c1 andthe sum signal s1 are input to the adder 2. At this time, since the sumsignal s1 is delayed by the memory 4 combinations of the carry signal c1and the sum signal s1 as shown in FIG. 2 are input to the adder 2. Theadder 2 outputs a carry signal c1 _(T1) and a sum signal s1 _(T1) attime T1 on the rising edge of a control signal, and outputs a carrysignal c1 _(T2) and a sum signal s1 ^(T2) at time T2. The adder 2 alsooutputs a carry signal c1 _(T3) and a sum signal s1 _(T3) at time T3.

When in this state, since the sum signals s1 _(T1)-s1 _(T3) are delayedby the memory 4, a combination of carry signal c1 _(T2) and sum signals1 _(T1) are input to the adder 2 at time T2, while a combination ofcarry signal c1 _(T2) and sum signal s1 _(T2) is input at time T3.

The adder 2 reads in carry signal c1 and sum signal s1 on the risingedge of the control signal and performs addition of the carry signal c1and the sum signal s1 before the next rising edge of the control signal.When adding the carry signal c1 and the sum signal s1 the adder 2follows the arithmetic rule shown in table 3 below.

TABLE 3 input internal sum (c1 + s1) value carry signal sum signal(−1) + (1) −1 0 −1 0 + 0 0 0 0 (−1) + 1 1 + 0 1 1 −1 0 + 1 1 + 1 2 1 0

Each of the digits of the carry signal c1 are values in the range“−1”-“1”, and each digit of the sum signal s1 is a value of “0” or “1”,which means that the addition result inside the adder 2 is in the range“−1” to “2”. When the addition result inside the adder 2 is “2”, theadder 2 sets the value of the carry signal c2 in the binary SD numbersystem to “1” and the value of the sum signal s2 to “0”. The adder 2outputs the carry signal c2 of value “1” to the adder 3 and outputs thesum signal s2 of value “0” to the memory 5. When the addition resultinside the adder 2 is “0”, the adder 2 sets the values of the carrysignal c2 and the sum signal s2 to “0”.

When the addition result inside the adder 2 is “−1”, the adder 2 setsthe value of the carry signal c2 to “0” and the value of the sum signals2 to “−1”, and when the addition result inside the adder 2 is “1”, theadder 2 sets the value of the carry signal c2 to “1” and the value ofthe sum signal s2 to “−1”. In this way, when the internal additionresult becomes “−1” or “1”, differing from adder 1 the adder 2 outputs“−1” as the value of the sum signal s2. The binary SD number system is aredundant number system, and the fact that one number can be representedin two ways is utilized in the adder 2.

The memory 5 and the memory 4 are the same. Specifically, the memory 5reads the sum signal s2 from the adder 2 on the rising edge of thecontrol signal d2. In this way the memory 5 delays the value of the sumsignal s2 by a single computing time unit of the control signal andoutputs the delayed sum signal s2 to the adder 3.

The adder 3 is a final stage, namely an output side, computing circuitinside the semiconductor circuit for arithmetic processing. The carrysignal c2 and the sum signal s2 are input to the adder 3. At this time,since the sum signal s2 is delayed by the memory 5 the sum signal s2outputted by the adder 2 one computation time unit before is input tothe adder 3.

The adder 3 reads in the carry signal c2 and the sum signal s2 in therising edge of a pulse of a control signal, and performed addition ofthe carry signal c2 and the sum signal s2 before the rising edge of thenext pulse. When adding the carry signal c2 and the sum signal s2, theadder 3 follows the arithmetic rule shown in table 4 below.

TABLE 4 input (c2 + s2) addition result output 0 + (−1) −1 −1 0 + 0 0 01 + (−1) 1 + 0 1 1

Values that can be used for the carry signal c2 are “0” and “1”, whilevalues that can be used as the sum signal s2 are “−1” and “0”, whichmeans that the addition result inside the adder 3 is in the range “−1”to “1”. The adder 3 outputs the internal addition result as it is asdata a3. That is, a carry signal representing carry in the binary SDnumber system is not included in the addition result of the adder 3.

Operation of the first embodiment will be described next.

Here, an example where data [100]_(SD) and data [00-1]_(SD) are added,specifically

[100]_(SD)+[00-1]_(SD)

will be described.

The two data items are

[100]_(SD) =[4]hd D

[00-1]_(SD)=[−1]_(D)

which means that the addition result will be a value of [3]_(D) in thedecimal system. Computation for this addition is carried out as follows.

As shown in FIG. 3, at time T1 of the control signal, “1” representingthe most significant digit of [100]_(SD) and “0 ” representing the mistsignificant digit of [00-1]_(SD) are input from the previous stagecircuit to the adder 1 as data a1 and data a2. As a result, the internaladdition result becomes “1” and so the adder 1 follows the arithmeticrule shown in table 2 to make the value of the carry signal c1 “0” andmake the value if the sum signal s1 “1”. The memory 4 receives “1” fromthe adder 1 and outputs this value at the next time T2. As a result, atthe point in time where the sum signal s1 having a value of “1” isreceived, the sum signal s1 having a value of “0” is output.

The adder 2 adds a value “0” of the carry signal c1 received from theadder 1 and a value “0” of the sum signal s1 received from the memory 4.As a result, the internal addition result becomes “0” which means thatthe adder 2 follows the truth able shown in table 3 to set the values ofboth the carry signal c2 and the sum signal s2 to “0”. The memory 5outputs value “0” received the previous time.

The adder 3 adds the value “0” of the carry signal c2 received from theadder 2 and the value “0” of the sum signal s2 received from the memory4. As a result, the internal addition result becomes “0” and so theadder 3 follows the arithmetic rule shown in table 4 and sets the valueof data a3 to “0”.

At time T1 of the control signal data a3 having a value of “0” is outputto the final stage circuit as a computation result for the mostsignificant digit.

At time T2 of the control signal, “0” representing second digit from themost significant digit in the data [100]_(SD), and “0” representing thesecond digit from the most significant digit in the data [00-1]_(SD),are input to the adder 1 from a previous stage circuit. In the same wayas for the case of time T1, adders 1-3 use the arithmetic rules 2-4, andthe memories 4 and 5 delay the values to add the second digits. As aresult, data a3 having a value of “1” is output to the final stagecircuit at time T2 of the control signal.

At time T3 of the control signal, “0” representing third digit from themost significant digit in the data [100]_(SD), and “−1” representing thethird digit from the most significant digit in the data [00-1]_(SD), areinput to the adder 1 from a previous stage circuit. In the same way asfor the case of time T1, adders 1-3 and the memories 4 and 5 add thethird digits. As a result, data a3 having a value of “−1” is output tothe final stage Circuit at time T3 of the control signal.

At time T4 of the control signal, in order to complete the computation,values of “0” are respectively input to the adder 1 as data a1 and a2 ofa previous stage circuit. As a result, data a3 having a value of “0” isoutput to the final stage circuit at time T4. At time T5 of the controlsignal, similarly in order to complete the computation, values of “0”are respectively input to the adder 1 as data a1 and a2 of a previousstage circuit. As a result, data a3 having a value of “−1” is output tothe final stage circuit at time T5.

Using T1 to T5, the value of data output to the final stage circuit bythe adder 3 becomes [01-10-1]_(SD). This data becomes [3]_(D) in thedecimal system, and so the correct result is output.

In this way, according to the first embodiment, when adding two dataitems, since a carry signal does not occur addition from the mostsignificant digit is possible. Specifically, by providing the memories 4and 5 as delay means, and with an extremely simple structure of onlycomputation circuits 1-3 for necessary digits, it is possible to carryout all addition processing from an upper order digit in single digit ormultiple digit units. That is, addition is realized with a small scalecircuit.

Also, first embodiment is not limited to addition from an upper orderbit, and includes subtraction, and all computations that require a carrysignal can be realized. Generally, information has more importantelements in the upper digits than in the lower digits, and so bycarrying out processing from the upper order digit it becomes possibleto acquires effective information earlier. Also, since there is acomputation circuit for one digit, there is also the advantage thatminiaturization is possible.

With the first embodiment, a binary SD number system is used for thevalues of data a1 and data a2, but it is also possible to use ordinarybinary. It is possible to use clock pulses as each, of the controlsignals. At that time, the memories 4 and 5 store values on the clockedge.

Addition is also possible with a decimal 11-valued redundant numbersystem, using a circuit structure similar to the first embodiment.Redundant numbers do not have to be negative, and there is no problem ifthey extend in a positive direction With the first embodiment, the adderwas a three stage structure, but if the adder is made having four ormore stages it is possible to realize an adder with multiple inputs froman upper order digit.

Further, a carry signal generated in a binary SD number system isconveyed to two upper order digits, but compared to the binary SD numbersystem, with a number system having a large degree of redundancypropagation of the carry signal is kept to one upper order digit. As aresult, to make the adder a two stage adder.

[Second Embodiment]

In the second embodiment, the adder 1 and the adder 2 of the firstembodiment are implemented as described in the following. Specifically,because of this two digit binary, comprising combinations of “0” and“1”, is used. According to two digit binary there are four combinationsof “0” and “1”. In the second embodiment, “0” in the binary SD numbersystem is expressed two ways in binary. Accordingly, “1”, “0” and “−1”in the binary SD number system is expressed as follows in binary.

“−1” in binary SD . . . [11]_(B)

“0” in binary SD . . . [00]_(B), [10]_(B)

“1” in binary SD . . . [01]_(B)

Using binary SD “1”, “0” and “−1” expressed in this way means the adder1 becomes as follows. For example, in the case of data a1 of “0” anddata a2 of “−1”, data a1 being a value of [00]_(B) and data a2 being avalue of [11]_(B) are input to the adder 1.

Inside the adder 1, if binary SD representation is used, the additionalresult is “−1”. In this case, In accordance with table 2, the value ofthe carry signal is “−1”, [11]_(B) is output as the carry signal and[01]_(B) is output as the sum signal.

In this way, when inputs are [00]_(B) and [11]_(B) in the case of adder1, outputs are [11]_(B) and [01]_(B). Further, based on othercombinations of inputs and outputs, the adder 1 can be constructed usingAND gates, OR gates and NOT gates.

There are various matches for “−1”, “0” and “1” constituting the binarySD number system in the binary system. Because of these matches,combinations are possible that are not limited to the AND, OR and NOT ofthe AND gates OR gates and NOT gates.

Also, besides a circuit structure using combinations of AND gates, ORgates and NOT gates, design is possible with combinations of otherlogical functions.

[Third Embodiment]

In the third embodiment, the adder 1 and the adder 2 of the firstembodiment have the following structure.

Specifically, the adder shown in FIG. 4 is used as the adder 1. Theadder 101 in FIG. 4 is comprised of neuron MOS inverters 101A-101C madeusing neuron MOS (Metal Oxide Silicon) transistors and inverters101D-101F.

The neuron MOS inverters 101A-101C are sequentially connected.

The output of the neuron MOS inverter 101A is connected to the of theneuron MOS inverter 101C and to the inverter 101F, the output of theneuron MOS inverter 101B is connected to the of the neuron MOS inverter101C and to the inverter 101E, and the output of the neuron MOS inverter101C is connected to the inverter 101D.

Data a4 and data a5 comprising 2 bits correspond to the data a1 and dataa2 in FIG. 1. A digit of a number in the redundant number system isrepresented by data a4 and data a5. Data a4 and data a5 can not beimplements using an electrical signal being transmitted on a singlesignal line. Accordingly, in order to implement data a4 and data a5 twosignal lines are required.

In the third embodiment, “−1”^(SD) is implemented as “00”_(B), “0”_(SD)is implemented as “10”_(B) and “1”_(SD) is implemented as “11”_(B). Withthese implementations, processing is extremely simple for neuron MOS.That is, when the number of “1”s on the two signal lines is 0 isrepresented by “−1”_(SD), when the number of “1”s is 1 is represented by“0” and when the number of “1”s is 2 is represented by “+1”_(SD). Therelationship between this information on the number of “1”s and theoriginal SD number, and the number of “1”s can be simply calculated inthe neuron MOS, by inputting respective signal lines to two equalcapacity input terminals.

A threshold value is provided in the neuron MOS inverters 101A and 101B.The threshold values are provided so as to invert the output whenaddition results are “−0.5” and “1.5”. By inverting respective outputsthe carry signal c3 is output. The redundant number of the carry signalc3 and the code of the electrical signal are the same a data a4 and dataa5. At the same time, the output of the neuron MOS inverter 101B isinput to the neuron MOS inverter 101C. Also, s3 corresponding to the sumsignal is output by the inverter 101D inverting the output of the neuronMOS transistor 101C. s3 corresponds to s1 in FIG. 1.

FIG. 5 is corresponds to the adder 2 in the first embodiment. The adderof FIG. 5 comprises neuron MOS inverters 201A and 201B. The neuron MOSinverters 201A and 201B are sequentially connected. The output of theneuron MOS inverter 201A is connected to the neuron MOS inverter 201Band the inverter 201C, and the output of the neuron MOS inverter 201B isconnected to the inverter 201D.

An intermediate sum component s3 and a carry signal c3 from a previousstage counter are added. When an internal addition result is “−0.5”, theoutput of the neuron MOS inverter 201A is inverted, and that output isinverted by the inverter 201C to output the carry signal c4. At the sametime, the addition result component s4 is output by inputting the outputof the neuron MOS inverter 201A to the neuron MOS inverter 201B. Theaddition result component s4 represents “−1” when at a low level andrepresents “0” when at a high level. c4 and s4 respectively correspondto c2 and s2 in FIG. 1.

The adder corresponding to the adder 3 in first embodiment is notrequired when using neutron MOS transistors. An intermediate sumcomponent s4 from the adder 201 is delayed by one computing time unit bya delay element. The carry signal c4 and the delayed addition resultcomponent s4 are output as a pair. The delay element is the memory 4 ofthe first embodiment. This pair output corresponds to a3 in FIG. 1, andcorrespondence between the redundant number and the two signal lines isthe same as the correspondence between a4 and a5.

In this way, if neuron MOS transistors are used it is possible toimplement a circuit extremely easily. Also, it is not limited to binarySD numbers, and it is also possible to implement a redundant adderhaving one delay element (propagation of carry signal to one upper orderdigit) by using a redundant adder with an increased radix, using aredundant adder with an increased number of inputs, called a 4-inputredundant adder or increasing the radix and the redundant number.

In the third embodiment, an inverter circuits is used as the basic gatefor neuron MOS transistor computation, but it is possible to provide anythreshold value and as long the output is in the format having binary“1”s and “0”s there is no limitation to an inverter circuit. Forexample, it is possible to use sense amplifier type logic circuits.

[Fourth Embodiment]

The fourth embodiment is an application of the present invention to asemiconductor circuit for arithmetic processing that calculates andoutputs the smaller of a difference between a first number and a secondnumber, and a difference between a third number and a fourth number.This semiconductor circuit for arithmetic processing is shown in FIG. 6.The semiconductor circuit for arithmetic processing of FIG. 6 comprisesdifference absolute value circuits 6 and 7, memories 8 and 9, and aminimum value circuit 10.

Data a6 representing one digit of the first number and data a7representing one digit of the second number are input to the differencecircuit 6. The data a6 and the data a7 are sequentially input to thedifference circuit 6 from the most significant digit. The differencecircuit 6 calculates a difference between the input data a6 and data a7and outputs a difference signal b6 representing the calculateddifference to the memory 8.

Similarly, data a8 representing one digit of the third number and dataa9 representing one digit of the fourth number are input to thedifference circuit 7. The data a8 and the data a9 are sequentially inputto the difference circuit 7 from the most significant digit. Thedifference circuit 7 calculates a difference between the input data a8and data a9 and outputs a difference signal b7 representing thecalculated difference to the memory 9.

The memories 8 and 9 are operated by a control clock c6. If D-typeflip-flops, for example, are used as the memories 8 and 9, the memories8 and 9 update stored contents using an edge trigger of the controlsignal c6. Specifically, the memories 8 and 9 output difference signalsb6, b7 for the previous single computation time unit to the minimumvalue circuit 10.

The minimum value circuit 10 outputs a signal according to a sizerelationship of the difference signals b6 and b7 from the memories 8 and9. Specifically, when the difference signal b6 is small compared to thedifference signal b7, difference signal b6 is output. This condition isa first condition. When the difference signal b7 is small compared tothe difference signal b6, the minimum value circuit 10 outputs thedifference signal b7. This condition is a second condition. Ifdifference signal b6 and difference signal b7 are the same, the minimumvalue circuit 10 can output either the difference signal b6 or thedifference signal b7. This condition is a third condition.

Until a reset signal is supplied to the minimum value circuit 10, theminimum value circuit 10 does not change from the first condition or thesecond condition.

Operation of the fourth embodiment will now be described in thefollowing.

The difference circuit 6 calculates a difference between data a6 anddata a7, and the difference circuit 7 calculates a difference betweendata a8 and data a9. Calculation results are output as differencesignals b6 and b7.

The difference signals b6 and b7 are input to the memories 8 and 9. ATthis time, the stored contents are updates using the control clock c6.Output from the memories 8 and 9 is a difference result for an upperorder digit, being the computation result for the previous time.Specifically, the memories 8 and 9 delay the difference signals b6 andb7 and operate to partition the digit information.

The memory 8 and the memory 9 output stored difference signal b6 and b7to the minimum value circuit 10. The minimum value circuit 10 thenselects the smaller value of the difference signal b6 and the differencesignal b7, and outputs the selected difference signal.

After that, using the next pulse of the control signal c6 the digits ofdata a6-a9 are transferred, computation moves to one digit lower andcomputation progresses in the direction from the upper order digits tothe lower order digits.

In this way, according to the fourth embodiment, it is possible tosequentially output the smaller difference value from the upper orderdigits. Normally, when determining a minimum value it is necessary tosequentially check from upper order digits within the digits making upthe data. As a result, the fourth embodiment is suitable for computationfrom an upper order digit.

Also, by arranging different computing elements in multiple stages it ispossible to implement combinations of complex computations.

This is one of the features of performing processing from an upper orderdigit. In the fourth embodiment, computation is in two stages, but it isalso possible to have more than two stages.

Further, it is not always necessary to have memory for partitioning andstoring digit information in each stage, they do not need to be providedin the output of the final stage.

[Fifth Embodiment]

In the fifth embodiment, this invention is applied to a semiconductorcircuit for arithmetic processing for calculating an absolute value of adifference. This semiconductor circuit for arithmetic processing isshown in FIG. 7. The semiconductor circuit for arithmetic processing ofFIG. 7 comprises a difference circuit 11, a forward and backwardrotation circuit 12, a state storage circuit 13 and a memory 14.

Data all representing one digit of a first number and data a12representing one digit of a second number are input to the differencecircuit 11. The data a11 and a12 are sequentially input to thedifference circuit 11 every computing time unit from the mostsignificant digit of digits making up the data.

The difference circuit 11 subtracts the input data a12 from the inputdata a11. The difference circuit 11 then outputs a carry signal b11generated by the difference calculation, and outputs a difference signalb12 represented the subtracted difference to the forward and backwardrotation circuit 12 and the state memory 13.

The state memory 13 stores the state of the difference signal b12. Thereare three state in the difference calculation. A state where a decisionas to which one of the data all or the data a12 is larger is entrustedto a lower order digit, a state where it has been decided that data allis larger, namely when the difference signal b12 is positive, and astate where it has been decided that the data a12 is larger, namely thatthe difference signal b12 is negative. Once it has been decided that oneof the data is larger, that state is not removed until processing iscompleted. The state memory 13 stores these three states. When the stateis that it has been decided that data a12 is larger, the state storagecircuit outputs a rotate instruction to the forward and backwardrotation circuit 12.

The forward and backward rotation circuit 12 obtains an absolute valueof the value of the difference signal b12. In order to do this, theforward and backward rotation circuit 12 uses the state of thedifference signal b12 stored in the state storage memory 13.Specifically, when the state is that data a12 is large, the differencesignal b12 is negative, and so the forward and backward rotation circuit12 rotates code representing the sign of each digit of the differencesignal b12. The forward and backward rotation circuit 12 thussequentially outputs an absolute value signal c11 representing theabsolute value of the calculated difference signal b12 from an upperorder digit.

The memory 14 is operated by a control circuit d11 and stores theabsolute value signal from the forward rotation circuit.

Using this fifth embodiment, the absolute value signal c11 stored in thememory 14 is output at the next clock of the control signal d11.Specifically, the absolute value signal c11 is delayed by onecomputation time unit. In this way, a carry signal b11 generated by thedifference circuit 11, and an absolute value signal c11 output by thememory 14 come to represent the same digit at the same time, and it iseasy to handle using an external circuit.

[Sixth Embodiment]

In the sixth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing which carries out anarbitrary operation from an upper order digit, then compares and decidesfrom an upper order digit, and omits arithmetic processing includingcomparison and decision for a remainder when authenticity has beendefined. This semiconductor circuit for arithmetic processing is shownin FIG. 8. This semiconductor circuit for arithmetic processing is acircuit for finding out the maximum from among a plurality of sets basedon an average value of two binary numbers, a delay circuit 22, acomparator 23 and a storage circuit 24.

Data a21 representing one digit of a first number and data a22representing one digit of a second number are input to the adders 21.The data a21 and a22 are sequentially input to the adder 21 from themost significant digit. The adder 21 adds tho input data a21 and a22,and outputs a sum signal representing the addition result to the delaycircuit 22. This adder is the circuit described in the first embodiment,and has internal delay means and does not generate a carry signal to theoutside.

The delay circuit 22 receives the sum signal b21 from the adder 21 anddelays the sum signal by one computation time unit using a control clockc21. When processing is performed from an upper order digit, the delayby one computation time unit is equivalent to a digit being delayed byone digit, specifically, to dividing a duodecimal number by two. Sincethe first data and the second data are binary numbers, delay by onedigit is the same as dividing by two, as a result of which an averagevalue is calculated. The delay circuit 22 outputs an average valuesignal d21 representing the average value to the comparator 23.

On the other hand, the storage circuit 24 stores a maximum average valuesignal d22 output by the comparator 23. Them when a control signal e22from the comparator 23 is OFF the currently stored average value signal,namely an average value signal representing a maximum of past averagevalues, is sequentially output from the most significant digit to thecomparator 23. When the control signal e22 from the comparator 23 is ON,the storage circuit 24 suspends output, and carries out preparation sothat from the next time a maximum average value is again outputsequentially.

The comparator 23 receives the average value signal d21 from the delaycircuit 22 and a past maximum average value signal from the storagecircuit 24 sequentially from an upper order digit. The comparatorcompares a value representing the average value signal d21 from thedelay circuit 22 and a value representing the past maximum average valuesignal From the storage circuit 24, and determines which is larger. Thecomparator 23 then outputs the larger average value signal to the memorycircuit sequentially from an upper order digit.

When two average value signals are being compared, if the maximum valueof average values from the past, namely a value representing an averagevalue from the storage circuit 24, is larger, then there are cases whereit is possible for the comparator 23 to make a decision. For example,according to the binary SD number system, an average value signal fromthe delay circuit being [00-1 . . . ]_(SD) corresponds to a case of theaverage value signal from the storage circuit having being [010 . . .]_(SD). In this case, the comparator 23 can confirm the comparisondecision at a point in time a certain number of digits from the nighorder. In this case the comparator 23 turns the control signal e22 ON.

At the point in time when the control signal e22 is turned ON, thecomparator 23 stops comparison decision for subsequent lower orderdigits, which means that output of the average value signal by thestorage circuit 24 is suspended and average value calculation andcomparison computation are suspended. Data transfer for all computationcircuits then returns to from the most significant digit, and the nextdigit data a21 and a22 are input.

Data are then sequentially compared from an upper order digit, thelarger ones among the compared results are output and if the maximumvalue can not be updated computational processing including comparisonof a digit having a comparison result and subsequent digits can beomitted. As a result, it is possible to realize computation that is notwasteful.

Also, by suppressing non-wasteful computation not only is it possible tospeed up the processing, but it also becomes possible to realize acircuit having low power consumption. This is particularly effectivewhen processing a large amount of data.

The type of computation is not limited to average values, and the typeof comparison and decisional computation is not limited to maximums, anda circuit for performing comparison or decision for any kind ofcomputational result is acceptable, for example a circuit for outputtinga value equal to or less than a difference value between two numbers.

Also, after the instruction to suspend computation, it is necessary tohave a data buffer before the data a21 and data a22 in order to rapidlyinput the subsequent data.

[Seventh Embodiment]

With the seventh embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing for computing a range ofvalises representing data and deciding whether or not the computedresults are in a specified range, This semiconductor circuit forarithmetic processing is shown in FIG. 9. The semiconductor circuit forarithmetic processing of FIG. 9 comprises an adder 26A for outputting amaximum value, ar adder 26B for outputting a minimum value, comparators27 and 28, and an AND gate 29.

The adder 26A for outputting a maximum value computes a maximum value,among values obtained using a lower order digit side, as a result ofaddition of data a26 and data a27 sequentially input from an upper orderdigit. The adder 26A then outputs a maximum value signal b26representing the computed maximum value.

The adder 26B for outputting a minimum value computes a minimum value,among values obtained using a lower order digit side, as a result ofaddition of data a26 and data a27. The adder 26B then outputs a minimumvalue signal b27 representing the computed minimum value.

The comparator 27 compares a predetermined upper limit value with themaximum signal b26 output from the adder 26A. When the result ofcomparison is that the value represented by the maximum value signal b26is small compared to the upper limit value, the comparator 27 outputslogical true to c26. When this is not the case, logical false is outputto c26.

The comparator 28 compares a predetermined lower limit value with theminimum signal b27 output from the adder 26B. When the result ofcomparison is that the value represented by the minimum value signal b27is large compared to the upper limit value, the comparator 27 outputslogical true to c27. When this is not the case, logical false is outputto c27. When both c26 and c27 are true, the value becomes “1”, while ifeither is false the value is “0”.

The AND gate 29 computes a logical and of the output c26 from thecomparator 27 and the output c27 from the comparator 28. When each ofthe comparators 27 and 28 output true, the AND gate 29 outputs true.Conversely, if either of the outputs c26 or c27 is false, the AND gate29 outputs false.

According to the seventh embodiment, as shown, for example, in FIG. 10,a decision is made as to whether or not an addition result is in aspecified range. In FIG. 10, a binary number system is assumed.Specifically, in the initial state, there is a possibility that therange of the maximum value computed by the adder 26A and the minimumvalue computed by the adder 26B is the entire range B1. In the eventthat the computation result of the most significant digit is “0”, arange that will be obtained using subsequent digits is from [011 . . .11]_(B) to [0000 . . . 0]_(B). Accordingly, the range B2 is a sectionobtained within the addition result. In this case, both of thecomparators 27 and 28 will be outputting false.

In the event that a computation result using data a26 and a27 for thenext digit down is “1”, the minimum value is updated to [010 . . . 0].In this case, the range B3 is a section obtained within the additionresult.

In the event that a computation result using data a26 and a27 for thenext digit down is “0”, the maximum value is reduced to [01011 . . . 1].In this case, the range B4 is a section obtained within the additionresult. At this time, the maximum value of range B4 is smaller than theupper limit value. Specifically, the comparator 27 outputs true.However, the comparator 28 outputs false, and so the overall outputremains at false.

If the computation result using data a26 and a27 for the next digit downbecomes “1” like the range B5, the minimum value becomes larger than theupper limit value. As a result, it will be known that the range B5 is ina specified range determined by the upper limit value and tile lowerlimit value, without computing subsequent lower order digits. In thiscase, both of the comparators 27 and 28 output true, and so the outputof the AND gate 29 is also true.

In this way, using seventh embodiment, it is possible to detect whetheror not a result of addition of data a26 and data a27 lies within aspecified range.

With the seventh embodiment, the adders 26A and 26B are used, but anycomputation is possible if there is a circuit structure capable ofdetecting a maximum value and a minimum value.

Also, as the comparison computation, it is possible to only compare withan upper limit value, or to only compare with a lower limit value.

Further, although not shown in the drawings, it is also possible todetect whether or not data is within a specified range by carrying out acomparison between the upper limit value and the minimum value, orcarrying out a comparison between the lower limit value and the maximumvalue.

[Eighth Embodiment]

With the eighth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing capable of switchingbetween computing functions. This semiconductor circuit for arithmeticprocessing is shown in FIG. 11. The semiconductor circuit for arithmeticprocessing shown in FIG. 11 comprises general purpose circuits 31 and 32capable of processing from an upper order digit, and a memory 33.

The general purpose circuit 31 is a circuit having a plurality offunctions that can be processed sequentially from upper order digits,such as an addition function from an upper order digit or a comparisonfunction from an upper order digit. One function among the plurality offunctions is selected using an instruction represented by the controlsignal c31. The general purpose circuit 31 processes input data a31 anda32 using the selected computation function. After processing, thegeneral purpose circuit 31 outputs data b31 representing a computationresult to the memory 33. The general purpose circuit 31 also out putsthe control signal b32 for an upper order digit, as required.

The general purpose circuit 32, similarly to the general purpose circuit31 is a circuit having a plurality of functions to be processedsequentially from upper order digits, such as an addition function or acomparison function. The general purpose circuit 32 selects one functionfrom among the plurality of functions using an instruction representedby the control signal c32. The general purpose circuit 32 processesinput data a33 and data b32 from the memory 33 using the selectedfunction.

The memory 33 delays the data b31 from the general purpose circuit 31 bya single computation time unit using a control clock d31. The memory 33then outputs the delayed data b32 to the general purpose circuit 32.

According to this eighth embodiment, it is possible to control acomputation function using control signal c31 and c32, and it ispossible to output a response according to an instruction representingby the control signals c31 and c32. That is, by supplying the controlsignals c31 and c32, it is possible to set any computation function.

The eighth embodiment is made up of two general purpose circuits and asingle memory, but the number of general purpose circuits and memories,or the combinations thereof, are not limited.

Also, a general purpose circuit can be realized by preparing a circuitfor carrying out each function, and can be realized with flexware usingneuron MOS transistors, but the general purpose circuit is notespecially limited.

Further, the control signals c31 and c32 can be the same or different.For example, continuous computation where control signal c31 representsan addition instruction and control signal c32 represents a comparisoninstruction is possible, and also an instruction for computingconsecutive digits by making c31 and c32 both addition instructions isalso possible.

[Ninth Embodiment]

In the ninth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing that carries out dataprocessing after analog to digital (A/D) conversion of an analog signalsequentially from an upper order digit, referred to generally as asuccessive approximation method. This semiconductor circuit forarithmetic processing is shown in FIG. 12. The semiconductor circuit forarithmetic processing of FIG. 12 comprises an A/D converter 36 and acomputing circuit 37.

The A/D conversion circuit 36 is means for converting an analog signalto a digital signal. The A/D conversion circuit 36 sequentially convertsto a digital signal from an upper order digit using a conversion methodgenerally referred to as the successive approximation method. Forexample, in the case of a binary number, the entire number ispartitioned into two regions, and it is determined which region an inputanalog voltage belongs to. If the result of determination is on the highvoltage side “1” is output, while if it is or the low voltage side “0”is output. Next, the region that the analog voltage belongs to isfurther divided into two regions, and it is determined which region theanalog voltage belongs to. Similarly, if it belongs in the high voltageside region “1” is output, while if it belongs in the low voltage sideregion “0” is output. By repeating these divisions and decisions, andmaking the range of the region in which the input analog voltage belongssuccessively narrower, sequential conversion is carried from the upperorder digit. The division and decision are performed every computingtime unit.

Conversion elements of the A/D converter 36 will be described in detailusing FIG. 13. The voltage level of an analog signal a36 input to theA/D converter 36 (hereinafter referred to as the input voltage) is thelevel shown by the dotted line. Initially, the A/D converter decideswhether the input voltage s larger or smaller than half the maximumamplitude. In this case, the full range A36 of the maximum amplitude isdivided into two smaller ranges, and it is determined whether the inputvoltage is in the minimum side half range or the maximum side halfrange. In this case, the input voltage is in the maximum side halfrange, and so the A/D converter 36 outputs a digital signal b36 with afirst bit of “1”.

After the next computing time unit, the maximum side half range A37 isfurther divided into two quarter ranges, and it is determined whetherthe input voltage is in the minimum side quarter range or the maximumside quarter range. In this case, the input voltage is in the minimumside quarter range and so the A/D converter 36 outputs the digitalsignal b36 having the second bit of “0”. Subsequently, in the samemanner, the A/D converter 36 outputs a result “1” for the third bit inthe quarter range A38, and outputs a result “1” for the fourth bit inthe eighth range A39 every computing time unit.

In this way, the A/D converter narrows the voltage range and convertsthe analog signal a36 to a digital signal b36. At this time, the A/Dconverter 36 outputs conversion results sequentially from the upperorder digit. This type of A/D conversion is already known, but a featureof this patent is that the computation circuit 37 matches from the upperorder digit and this conversion is synchronized with this computationcircuit 37.

Also, if the A/D converter 36 receives the control signal b37 from thecomputing circuit 37 A/D conversion of the analog signal 36 a from theupper order digit is suspended.

If the computing circuit 37 receives the digital signal 36 b output fromthe A/D converter 36, computing set in advance is carried out for thedigital signal b36. If the computing circuit 37 then determines thatthere is no need to convert the analog signal a36 to the digital signalb36, based on the computational result, a control signal b37representing suspension of conversion is output to the A/D converter 36.Determination that conversion is not required will be the result when,for example, the conversion precision required by the A/D converter hasbeen obtained at that time, or when the authenticity of anydetermination stage is confirmed.

According to the ninth embodiment, by returning the control signal b37to the A/D converter 36 analog to digital conversion is suspended midwaythrough, and it is possible to input the next analog signal. As aresult, wasteful conversion is curtailed, the average conversion rate isimproved and there is the advantage that power consumption is reduced.

In the ninth embodiment, the voltage range is narrowed by half in orderto obtain an output per bit (binary number) as a digital signal b36, butin the case of output per plurality of bits, it is possible to dividethe voltage range by ½^(N) and make a decision as to which range theanalog signal is in order to obtain output every N bits.

[Tenth Embodiment]

In the tenth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing using a bus that cantransmit data having a flexible bit width. This semiconductor circuitfor arithmetic processing will be described using FIG. 14. In FIG. 14,memories 41A and 41B are bit-sequential memories. Specifically, thememories 41A and 41B store a plurality of data items, and the data areoutput to a data buses 42A and 42B every digit of a computation unit. Atthis time, the memories 41A and 41B sequentially output data every digitfrom upper order digits to lower order digits. That is, for a binarynumber, the memories 41A and 41B have such a structure that stored datais output sequentially one bit at a time from upper order bits to lowerorder bits. The memories 41A and 41B can be made of, for example, shiftregisters.

A semiconductor circuit for arithmetic processing 43 that is connectedto the memories 41A and 41B through data buses 42A and 42B is acomputing circuit or computing unit for sequentially processing datafrom the upper order digits.

The data buses 42A and 42B are preferably 1 bit wide per one data item.Specifically, the bus width of the data buses 42A and 42B corresponds tothe number of data items simultaneously read out from the memories 41Aand 41B (=degree of parallelism).

In this way, compared to a conventional bus width which is the data bitwidth or a multiple of the data bit width, according to the tenthembodiment the overall bus width can be made the number of data itemssimultaneously read out from the memories 41A and 41B.

With the tenth embodiment, a description has been given where a singlebit unit has been adopted as the computation unit, but it goes withoutsaying that the present invention is not limited to this and can adopttwo or more bits as the computation unit.

Also, a single circuit is used as the semiconductor circuit forarithmetic processing 43, but it does not especially have to be a singlecircuit as long as it is a semiconductor circuit for arithmeticprocessing for processing sequentially from an upper order digit.

[Eleventh Embodiment]

In the eleventh embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing for carrying outmultiplication from an upper order digit using addition from the upperorder digit. This semiconductor circuit for arithmetic processing isshown in FIG. 15. The semiconductor circuit for arithmetic processing ofFIG. 15 comprises shift registers 45A-45H, partial product generatingcircuits 46A-46H, and redundant adders 47A-47D, 48A, 48B and 49.

The shift registers 45A-45H are together assumed to constitute as 8 bitmultiplier, and are located at 8 places. On a clock edge, data inputfrom an upper order byte are sequentially shifted so that the contentsof shift register 45G are shifted into shift register 45H, the contentsof shift register 45F are shifted into shift register 45G, the contentsof shift register 45E are shifted into shift register 45F, and so on,and multiplier information for a new digit is input to shift register45A This data is sequentially input from the most significant digit ofdata representing the multiplier to the shift register 45A. The shiftregisters 45A-45H output the stored multiplier data to the partialproduct generating circuits 46A-46H. For example, in the initial stepthe most significant digit of multiplier data is input to the shiftregister 45A, and data is output to the partial product generatingcircuit 46A. “0” is stored in the remaining shift registers 45B-45H. Inthe next step, the most significant digit is stored in shift register45B, data of the second digit from the most significant digit is storedin shift register 45A, and the data are respectively output to thepartial product generating circuits 46A-46B.

The partial product generating circuits 46A-46H are a times partialproduct generating circuits for 8 bit multiplication, and computepartial products of a multiplier output from the shift registers 45A to45H, and a multiplicand having all bits input at the same time. Themultiplicand is arranged so that the most significant digit is input to46 a and the least significant digit is input to 46H. Then, the partialproduct generating circuits 46A-46H output the partial products of thesame digit in the multiplication to the adding circuits sequentiallyfrom the most significant digit.

The redundant adders 47A-47D, 48A, 48B and 49 are connected in atree-like configuration. With this tree-like connection, the redundantadders 47A-47D, 48A, 48B and 49 add the partial products generated bythe partial product generating circuits 46A-46H and output a singlemultiplication result sequentially from the upper order digit using thefinal redundant adder 49.

With this type of structure, as shown in FIG. 16, multiplication isimplemented by expanding multiplication as if it were worked out onpaper and generating and adding a string of partial products with thepartial products to be added being vertically separated. In FIG. 16, therange of the vertically divided partial products is shown as range A45.From the partial product generating circuits 46A-46H a number input toeight frames inside the range A45 are output at the same clock. Therange A45 is transferred to the lower order digit (to the right in FIG.16) every single step (computation time unit), and partial products forone lower order digit are sequentially generated from the upper orderdigits to the lower order digits. Using the redundant adders 47A-47D,48A, 48B and 49, partial products from the upper order digit generatedby the partial product generating circuits 46A-46H are added up, and itis thus possible to obtain a multiplication result from the upper orderdigit.

In this way, according to the eleventh embodiment, by adding from theupper order digit it is possible to carry out multiplication from theupper order digit.

In the eleventh embodiment, for simplicity, 8 partial products aregenerated for multiplication in 8 bit units, but it is possible to thenumber of partial products generated at the same time using a generallyused booth decoder.

Also, two-input single-output type adders have been used as theredundant adders 47A-47D, 48A, 48B and 49, but any adder that can carryout addition from the upper order digits is permissible, for example afour-input single-output redundant adder or the like.

Further, in the eleventh embodiment an 8-bit multiplier has beenexemplified, but the present invention is by no means limited to 8-bits,and 16-bit or any other number of bits are possible. In the case of16-bit multiplication, as a general rule, 16 partial products will begenerated.

[Twelfth Embodiment]

The twelfth embodiment is a modified example of the eleventh embodiment.In the twelfth embodiment the present invention is applied to asemiconductor circuit for arithmetic processing for carrying outinformation aggregating processing besides multiplication, such asretrieval. This semiconductor circuit for arithmetic processing is shownin FIG. 17. The semi conductor circuit for arithmetic processing of FIG.17 comprises general purpose functional units 51A-51H, 52A-52D, 53A, 53Band 54.

With the twelfth embodiment, the general purpose functional units51A-51H, 52A-52D, 53A, 53B and 54 are connected in a tree configuration.The general purpose functional units 51A-51H are controlled by a controlinstruction b51, and the general purpose functional units 52A-52D arecontrolled by a control instruction c52. The general purpose functionalunits 53A and 53B are controlled by a control instruction d53.

For example, the general purpose functional units 51A-51H performcomputation processing designated by the control instruction b51 on dataa51 ₁-a51 ₁₆. Specifically, if the general purpose Functional units51A-51H, 52A-52D, 53A, 53B and 54 have a function of performing additionfrom an upper order digit, they will achieve the same function as theeleventh embodiment. If the general purpose functional units 51A-51H,52A-52D, 53A, 53B and 54 are circuits for outputting a maximum valuefrom an upper order digit, a maximum value is output from the generalpurpose functional unit 54.

In this way, according to the twelfth embodiment information narrowingand information aggregation are carried out, and in this way it ispossible to narrow down a lot of information to a single informationitem. That is, processing for other information aggregation besidesmultiplication, such as retrieval, becomes possible. Also, since, due tothe principal of computing from the upper order digit, the generalpurpose functional units 51A-51H, 52A-52D, 53A, 53B and 54 can carry outprocessing for a single digit, it is possible to miniaturize thecircuitry, and it is also possible to improve the degree of parallelismin the circuit overall.

With the twelfth embodiment, 16-input circuits have been described, but16 inputs are not strictly necessary and it possible to have, forexample, 8 inputs or 32 inputs.

[Thirteenth Embodiment]

In the thirteenth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing for realizingmultiplication from an upper order digit by repeated addition. Thissemiconductor circuit for arithmetic processing is shown in FIG. 18. Thesemiconductor circuit for arithmetic processing of FIG. 18 comprisespartial product generating circuits 55A-55D, unitary delay memories 56Aand 56E, adders with built-in delay memory 56B-56D, and a redundantadder 57. Here, a 4-bit multiplier is exemplified.

A multiplicand a55 is input to the partial product generating circuits55A-55D. At this time, the most significant digit data of themultiplicand a55 is input to the partial product generating circuit 55D,data of the digit below the most significant digit is input to thepartial product generating circuit 55C, data of the digit two digitsdown from the most significant digit is input to the partial productgenerating circuit 55B, and data of the least significant digit is inputto the partial product generating circuit 55A. A multiplier a56 is alsoinput to the partial product generating circuits 55A-55D. The multipliera56 is simultaneously input to the partial product generating circuits55A-55D sequentially one digit at a time in computation time units fromthe upper order digit. The partial product generating circuits 55A-55Dgenerate partial products from the multiplicand a55 and the multipliera56.

Partial products from the partial product generating circuits 55A-55Dare subjected to addition processing by the memory 56A and the adderswith built-in memory 56B-56D. As a result, the adder 56B adds a partialproduct from the partial product generating circuit 55A delayed by thememory 56A, and the partial product from the partial product generatingcircuit 55B, and outputs a carry signal b55 and a sum signal b65 on thenext rising edge of control signal 55 e. That is, there is a function ofstoring a computation result internally, and delaying it by one step(computational unit time). The adder with built-in memory 56C adds avalue “0”, a partial product from the partial product generating circuit55C, and a sum signal b56 of the adder with built-in memory 56B, andoutputs a carry signal c55 and a sum signal c56 on the next rising edgeof the control signal 55 e.

The adder 56D adds a carry signal b55 from the adder 56 b for adding thetwo lower order digits, a partial product from the partial productgenerating circuit 55D, and a sum signal from the adder with built-inmemory 56C, and outputs a carry signal d55 and a sum signal d56 on thenext rising edge of the control signal 55 e. The memory 56E delays thecarry signal c55 from the adder 56C for adding two lower order digitsand a sum signal of the adder with built-in memory 56D, and outputs themto the redundant adder 57.

The memories 56A and 56E, and the adders with built-in memory 56B-56Dleft shift data one digit at a time towards the redundant adder 57 side,under the control of a control clock e55. Also, the memory 55E isrequired to convert the carry signal d55 generated by the adder withbuilt-in memory 56D and another result to the same digit.

The redundant adder 57 performs addition from an upper order digit usingthe carry signal d56 from the adder 6 delayed by the memory 56E, thecarry signal c55 from the adder with built in memory 56C, and the carrysignal d55 from the adder 56D. This adder has substantially the samedesign as the upper order digit preceding adder disclosed in the firstembodiment for a binary SD number system. Besides the two inputs of theSD system to the adder 1, the inputs to the binary system have beenincreased by one. It is possible to include a condition for outputtingCarry+1 and Sum 1 when the internal sum value of table 2 is +3. In thisway, multiplication results are output sequentially from an upper orderdigit.

According to the thirteenth embodiment, as shown in FIG. 19, in the caseof 4-bit×4-bit multiplication, partial products are generated in thesame format as if it were worked out on paper, and these are added.

The adding line section 56 is a simple representation of the addingarrangement for this multiplication method. In the adding section 56,“+” symbols enclosed in a circle represent adders that can carry outaddition from an upper order digit, and the symbol “D” enclosed in asquare represents a memory. The memory stores input data every onecomputation time unit. The “+” symbols and “D” symbols are arranged inpairs, but correspond to 56B-56D in FIG. 18. In order to add thesepartial products, the memories D are previously reset to “0”. In thefirst step, data representing the lowest line A55 of a calculation as ifit were worked on paper is input to the adding section 56, and this datais stored.

At a second timing, data input from the memory “D” is left shifted(multiplied by 2). At the same time, data representing the line two fromthe bottom A56 is input to the adding section 56, and the input data anddata being stored in the adding section 56 are added. Data stored in theadding section 56 is obtained by shifting previous line A55.

At a third timing, the addition result obtained at the second timing isleft shifted and stored. After that, the upper line is also addedrepeatedly to output a final result.

In this way, according to the thirteenth embodiment when multiplicationis implemented by repeating addition, result can be output from a finalstage, and from an upper order digit.

In the thirteenth embodiment, 4-bit×4-bit multiplication has beenassumed, there is no particular limitation to 4-bits. Whenmultiplication of greater than 4-bits is performed, it is possible tosimply increase adders having built-in memory having three inputs of thepartial product data from the partial product generating circuits, thecarry data from the adder two digits below and the addition sum datafrom the adder one digit below, like the adder with built-in memory 56D.

It is also possible to have combinations of already known decodetechniques, such as both decoders.

In FIG. 18, the structure is such that carry data is input to the addertwo digits above order digits because a carry signal of the adders56B-56D is delayed, but it is also possible to remove this delay memoryand directly input carry data to an adder one digit above.

Further, with multiplication from an upper order digit, the numbersystem used is not limited to the binary system or the binary SD system.

[Fourteenth Embodiment]

In the fourteenth embodiment, addition computation from an upper digitis carried out using a general number system is used and not a redundantnumber system. For this reason, in the fourteenth embodiment a flagrepresenting whether a number that is the object of computation isdefined or indeterminate is provided. This element is shown in FIG. 20.In FIG. 20, a decimal addition of [2999]_(D)+[902]_(D)=[3901]_(D) isexemplified. In this addition example, a carry generated in the lowerorder digit is propagated from the units column to the hundreds column.

At time T71, numbers in the thousands column are added and a value of[2]_(D) is obtained. There is a possibility that this value [2]_(D) willbe changed by a carry signal from a lower order digit. At this time, theflag can be attached to the value [2]_(D). In the fourteenth embodiment,a question mark, namely “?” is used as the flag.

At time T72, the numbers in the hundreds column are added, and a value[18]_(D) is obtained. With this value [18]_(D) a value [1]_(D) isgenerated as a carry signal, and a sum signal has a value of [8]_(D).The carry signal [1]_(D) updates the value [2]_(D) in the thousandscolumn to [3]_(D).

Here, the sum signal value [8]_(D) has no effect on signals at or belowthe lower tens column, and does not constitute a carry signal to thethousands column. For this reason, the “?” mark attached to the numberin the thousands column is removed and the value [3]_(D) is defined.

At time T73, numbers in the tens column are added and a value of[09]_(D) is obtained. With this value [09]_(D) the carry signal has avalue of [0]_(D). There is a possibility that the carry signal value[0]_(D) or the sum signal value [9]_(D) will be updated by thecalculation result of the units column. For this reason, the carrysignal value [0]_(D) in the addition result, and the sum signal value[9]_(D) both have the mark “?” attached.

Accordingly, since the carry signal from the tens column has not beendefined, the “?” mark attached to the value [8]_(D) of the sum signalfor the hundreds column is propagated without being removed.

At time T74, numbers in the units column are added and a value [11]_(D)is obtained. With this value [11]_(D), a value [1]_(D) is generated as acarry signal, and the sum signal is a value [1]_(D).

The value [1]_(D), being the carry signal for the units column, is addedto the value [9]_(D), being the sum signal for the tens column. As aresult, a value [10]_(D) is obtained in the tens column, and a value[1]_(D), being the carry signal, is generated. This carry signal isadded to the value [8]_(D) being the sum signal for the hundreds column.

The carry signal is then propagated to the hundreds column and the tenscolumn. Since the carry signal from the units column is defined as[1]_(D), the values of the sum signal of the tens column, the carrysignal from the tens column and the sum signal from the hundreds columnare all defined. These operations are repeated to sequentially outputdefined values and a value of [3901]_(D), being the correct additionresult, is obtained. In FIG. 20, the digits that will be output areunderlined.

A semiconductor circuit for arithmetic processing for doing this isshown in FIG. 21. With this semiconductor circuit for arithmeticprocessing a signal corresponding to a flag only in the carry signal(the “?” mark in FIG. 20) is added as a state signal. The semiconductorcircuit for arithmetic processing of FIG. 21 comprises an adder 61,carry control circuits 62 and 62, and respective delay elements 61 m, 62m and 63 m.

The adder 61 adds one digit of data a61 input from r digit of a firstnumber and one digit data a62 input from an upper order digit of asecond number. The adder 61 outputs a carry signal b61 and a sum signalb62 as a result. The adder 61 also outputs a state signal b63. The statesignal b63 indicates whether or not there is a possibility of the carrysignal b61 being generated. If the state signal b63 is true, itindicates that there is a possibility of the carry signal b61 beinggenerated. The sum signal b62 is delayed by one step (computation timeunit), namely delayed by one digit, by the delay element 61 m, andstored.

The carry control circuit 62, as shown in FIG. 22, comprises a statecontrol circuit 601 and an output circuit 603. The carry control circuitdecides whether or not a carry is needed, in accordance with the carrysignal b61, and the state signal b63 and the delayed addition resultb62, and changes the result as required. To make the decision, the carrycontrol circuit has an input output relationship as shown in thefollowing table 5 internally stored.

TABLE 5 input result 0-8 9 component carry 0 0 1 0 0 1 component statesignal ? fixed fixed ? fixed fixed output result 0-8 1-9 9 9 0 componentcarry 0 0 0 0 1 component state signal fixed fixed ? fixed fixed

In accordance with table 5, processing is different depending on theinput addition result b12.

When the input addition result b12 is a value of “0”-“8”, there is nopossibility of carry signal propagation to the upper digit, and so thestate control circuit 601 outputs a carry signal c61 representing thevalue “0”, and a state control signal c63 representing “fixed”. Theoutput circuit 603 outputs the input addition result signal b62 and aresult component c62 representing the same value when the input carrysignal b61 has a value “0”, and when the input carry signal b61 has avalue “1” outputs a result component c62 representing a value of “1”added to the input addition result signal b62.

When the input addition result b12 has a value of “9”, the state controlcircuit 601 outputs carry data c61 representing a value the same as theinput carry data b61, and a state signal c63 representing a value thesame as the input state signal c63. When the input carry signal b61 hasa value of “1”, a result component c62 having a value of “0” is output,and when the input carry signal b61 has a value of “0” a resultcomponent having a value of “9” is output.

The state signal c63 generated in this way is output to the carrycontrol circuit 63 by the carry control circuit 62. The carry controlcircuit 62 also generates a carry signal c61 from the carry signal b61and the sum signal b62. The carry control circuit 62 then outputs thegenerated carry signal c61 to the carry control circuit 63.

The output circuit 603 generates a sum signal c62 based on the sumsignal b62 from the memory 61m and the carry signal b61. Specifically,the output circuit 603 adds the value of the carry signal b61 to a sumsignal b62 from the memory 602, namely a stored value, as shown in table3, and generates the sum signal c62. The output circuit 603 outputs thegenerated sum signal c62 to the carry control circuit 63.

The carry control circuit 62 thus generates the carry signal c61, thesum signal c62 and the state signal c63 based on the carry signal b61,the sum signal b62 and the state signal b63, and outputs these signalsto the carry control circuit 63. In a similar manner, the carry controlcircuit 63 generates a carry signal d61, a sum signal d62 and the statesignal d63 based on the carry signal c61, the sum signal c62 and thestate signal c63, and outputs these signals to a final stage circuit 63.

According to the fourteenth embodiment, the output of the carry controlcircuit 62 constitutes the input of the carry control circuit 63 havingthe same function. By connecting a plurality of stages in this way, itis possible to propagate a carry across a plurality of stages, forexample, when calculating [999+001]_(D), and changes occurring becauseof the carry can be absorbed.

Thus, according to the fourteenth embodiment, in order to process thecarry signal, when the calculated value is indeterminate and there is apossibility that it will be changed later the mark “?” is attached. Inthis way, it is possible to remove the influence of the carry. Also,according to the fourteenth embodiment, since there is a binary outputit is possible to increase affinity with a current circuit.

In the fourteenth embodiment a decimal number has been used as thecomputation example, but it is not limited to a decimal number andbinary or the like can also be used.

[Fifteenth Embodiment]

In the fifteenth embodiment, the present invention is applied to asemiconductor circuit for arithmetic processing for converting data of aredundant number system to data in a non-redundant number system. Thissemiconductor circuit for arithmetic processing is shown in FIG. 23. Thesemiconductor circuit for arithmetic processing of FIG. 23 comprises aredundant conversion circuit 66, carry processing circuits 67 ₁-67 _(n),and memories 68 ₁-68 _(n). With the semiconductor circuit for arithmeticprocessing of FIG. 23, at the time of the worst input pattern there is apossibility that a carry will be generated, from the least significantdigit to the most significant digit, which means that it is necessary tohave circuits for several digits for both the redundant conversioncircuit and the carry processing circuits 67 ₁-67 _(n).

Data a66 representing one digit of a number belonging to a redundantnumber system is input to the redundant conversion circuit 66. The dataa66 is input sequentially from the upper order digit every computationtime unit.

When the data a66 is input, the redundant conversion circuit 66 convertsthe data a66 to data of a non-redundant number system and outputs thedata b67. As a result, the redundant conversion circuit 66 generates acarry signal b66 as required. In order to perform this type ofconversion, the redundant conversion circuit 66 internally holds theinput relationship shown in table 6 below.

TABLE 6 input data 1 0 −1 output carry signal 0  0? −1 conversion 1 0 1result

According to FIG. 6, when “1” is input as data a66 the redundantconversion circuit 66 generates a carry signal (Carry) b66 of “0” and aconversion result (Result) b67 of “1”. When “−1” is input as data a66,the redundant conversion circuit 66 generates a carry signal b66 of “−1”and a conversion result b67 of “1”. Specifically, in order to ensurethat the conversion result is in a non-redundant number system, theredundant conversion circuit 66 generates a carry signal b66 of “−1” inthe case of a binary SD number.

The redundant conversion circuit 66 also attaches a signal, being themark “?”, when there is a possibility that the value of the carry signalb66 will be changed by the carry signal from the lower order digit. Thatis, when “0” is input as data a66, the redundant conversion circuit 66generates a carry signal b66 of “0?” and a conversion result b67 of “0”.

The redundant conversion circuit 66 outputs the generated carry signalb66 to a carry processing signal 67 ₁, and outputs the conversion resultb67 to the memory 68 ₁.

The memory 68 ₁ delays the conversion result b67 from the redundantconversion circuit 66 by one step (computation time unit) using thecontrol clock d66. The memories 68 ₂-68 _(n) have a function of causingthe input data to be delayed by one computational time unit, similarlyto the memory 68 ₁.

The processing circuit 67 ₁ receives as input the carry signal b66coming from the lower order digit, and a conversion result b68 that isthe conversion result b67 delayed and output by the memory 68 ₁, andconverts them. In order to perform this conversion, the carry processingcircuit 67 ₁ internally holds the input output relationship shown intable 7 below.

TABLE 7 input conversion 0 0 0  1 1 1 result carry signal −1 0 0? −1 0 0? output carry signal −1 0 0? 0 0 0 conversion 1 0 0  1 1 1 result

In accordance with table 7, when there is no “?” mark attached to thecarry signal b66, the carry signal components becomes defined. As aresult, there is no need for recalculation by the circuits on the upperdigit side, and it is possible to determine the computation result.

When there is “?” mark attached to the carry signal b66, then if thecarry signal b66 is “0?” and the conversion result b68 is “0” the carryprocessing circuit 67 ₁ generates a carry signal c66 of “0?” and aconversion result c67 of “0”. Also, if the carry signal b66 is “0?” andthe conversion result b68 is “1” the carry processing circuit 67 ₁generates a carry signal c66 of “0” and a conversion result c67 of “1”.

The carry processing circuit 67 outputs the carry signal c66 generatedin this way to the carry processing circuit 672 of the next stage, andoutputs the conversion result c67 to the carry processing circuit 67 ₂of the nest stage via the delay memory 68 ₂. The carry processingcircuit 67 ₂-67 _(n) perform similar the carry processing circuit 67 ₁.

According to this fifteenth embodiment, it is possible to convert datain a redundant number system to data in a normal non-redundant numbersystem.

With the fifteenth embodiment, a case where a binary SD number in aredundant number system is converted to a binary number has beendescribed as an example of computation processing, but the presentinvention is not particularly limited to this number system and it ispossible to use a multi-value redundant number system such as base-4 oroctal (base-8), and it is also possible to make an expanded numberpositive.

First to fifteenth embodiments have been described above, but thepresent invention is not limited to these embodiments. For example,“digit” does not have to be a decimal number and it possible to useunits of “bits” in a binary system, and to use groups of bits in abase-4 number system.

Also, an addition instruction has been taken as an example of acomputation instruction, but any computation instruction is possible aslong as computing can be performed every digit, such as a subtractinstruction or a compare instruction.

As a redundant number system, the present invention does not have to belimited to a system that allows “−1” in a binary number “0, 1”, such asthe binary SD number system, and it is also possible to use systems suchas 11-valued decimal (as well as “0-9”, “A=10” is permitted) or 3-valuesbinary (“2” is permitted in “0, 1”).

It is also possible to replace transistors in all circuits implementedwith conventional transistors with neuron MOS transistors.

Industrial Application

According to the present invention it is possible to realize a circuitfor processing data from information of an upper order digitrepresenting more important information.

According to one form of the present invention it is possible to realizea semiconductor circuit for arithmetic processing of a plurality ofgroups from an upper order digit.

According to another form thereof the present invention it is possibleto obtain a semiconductor circuit for arithmetic processing that canabsorb a propagation signal from a lower order digit such as in additionprocessing by using a redundant number system, and that enablesarithmetic processing from an upper order digit.

According to yet another form of the present invention it is possible torealize a semiconductor circuit for arithmetic processing from acomplete upper order digit with no carry signals at all, looking fromoutside the circuit.

According to still another form of the present invention a semiconductorcircuit for arithmetic processing from an upper order digit that vanprocess a carry signal from a lower order digit without using aredundant number system is also made possible.

According to one form of the present invention it is possible to realizea semiconductor circuit for arithmetic processing that can omit lowerorder digit side computation from digits for which there is a resultdecision.

According to another form of the present invention it is possible toobtain a semiconductor circuit for arithmetic processing capable ofcomputational comparison decision from an upper order digit, that is notdependent on a signal from a lower order digit based on a minimum valueand a maximum value.

According to one form of the present invention it is possible to realizea semiconductor circuit for arithmetic processing for processing from anupper order digit aimed at a general purpose processor, or asemiconductor circuit for arithmetic processing that can vary a functionin real-time while having simple hardware.

According to yet another form of the present invention it is possible torealize a semiconductor circuit for arithmetic processing that canbinary convert a redundant number system from an upper order digit.

According to still another form of the present invention it is possibleto realize a semiconductor circuit for arithmetic processing that cancarry out processing from sequential upper order digits for a compactanalog signal.

According to one more form of the present invention it is possible torealize a semiconductor multiplier that outputs a result from an upperorder digit.

According to yet another form of the present invention it is possible torealize a semiconductor multiplier from an upper order digit usingdifferent techniques.

According to another form of the present invention a processing circuitfrom an upper order digit introducing a concept of intelligentcomputation, that reduces the scale of a circuit and increases computingunctions, by using neuron MOS transistors.

According to one form of the present invention it becomes possible touse a method capable of arithmetic processing from an upper order digitby using a redundant number system.

According to another form of the present invention a high speedprocessing method becomes possible that can omit remaining computationat a point in time where a computation from an upper order digit hasbeen defined.

What is claimed is:
 1. A semiconductor circuit for arithmeticprocessing, being a semiconductor circuit receiving as input at leastone numerical data item comprised of a plurality of digits, inputsequentially one digit per computing time unit from the upper digit ofthe numerical data, provided with a computing unit for computing of theinput data, the computing unit comprising: a computing circuit, forcomputing input digit data within a computing time unit, and outputtinga computation result representing a result obtained by the computationto generate a carry using the computation and outputting carry datarepresenting this carry; and delay means for delaying the computationalresult from the computing circuit by only a single computing time unit.2. The semiconductor circuit for arithmetic processing of claim 1,wherein a plurality of the computing units are connected in series, andeach of the computing units performs processing sequentially everycomputation time unit.
 3. The semiconductor circuit for arithmeticprocessing of claim 2, wherein the computing unit comprises: firstdecision means for deciding whether or not carry data output to an upperdigit as a result of computation of a particular digit is changed usingcarry data generated by computation for a lower digit than that digit;output means for indicating that there is no change to carry data to anupper order side, when a decision result from the first decision meansindicates that there is no dependency on carry data output from thelower order digit; input means for holding lower order side carry data,when the decision result from the first decision means indicates thatthere is dependency on carry data output from the lower order is digit;and changing means for changing a computational result in response tolower order digit carry data from the lower order side.
 4. Thesemiconductor circuit for arithmetic processing of claim 1 wherein thenumerical data, the computational result or the carry data belong to aredundant number system.
 5. The semiconductor circuit for arithmeticprocessing of claim 4, wherein a computing block for computing databelonging to the redundant number system comprises at least one of thecomputing units and a computing circuit for processing output of thecomputing block, and carry data to an upper order digit is not generatedfrom the computing block.
 6. The semiconductor circuit for arithmeticprocessing of claim 1 wherein the computing unit comprises: firstdecision means for deciding whether or not carry data output to an upperdigit as a result of computation of a particular digit is changed usingcarry data generated by computation for a lower digit than that digit;output means for indicating that there is no change to carry data to anupper order side, when a decision result from the first decision meansindicates that there is no dependency on carry data output from thelower order digit; input means for holding lower order side carry data,when the decision result from the first decision means indicates thatthere is dependency on carry data output from the lower order digit; andchanging means for changing a computational result in response to lowerorder digit carry data from the lower order side.
 7. The semiconductorcircuit for arithmetic processing of claim 6, wherein a computing blockconverts data sequentially input from an upper order digit everycomputing time unit to a non-redundant number system when data belongsto a redundant representation and if conversion is necessary, conversionmeans for converting to a non-redundant representation and a carrysignal, or a borrow signal, and output means for outputting the carrysignal or the borrow signal to a computing unit for an upper orderdigit, the semiconductor circuit for arithmetic processing having anoverall function of converting a redundant number system to anon-redundant number system.
 8. The semiconductor circuit for arithmeticprocessing provided in claim 1 further comprising: decision means forcomparing and deciding, for every computing time unit from an upperdigit, computational results output sequentially every computing timeunit from the upper digit, wherein when authenticity of the decisionresult of the decision means has been confirmed, arithmetic processingincluding comparison and decision for remaining lower order digits isomitted.
 9. The semiconductor circuit for arithmetic processing of claim8, further comprising: computing means for sequentially carrying outcomputation every computing time unit from an upper digit side andcomputing a maximum value and a minimum value for computational resultsacquired at a lower digit than an input digit; and comparison means forcomparing at least one of the maximum value and the minimum valuecomputed by the computing means with data of another digit.
 10. Thesemiconductor circuit for arithmetic processing of claim 1, furthercomprising: computing means for sequentially carrying out computationevery computing time unit from an upper digit side and computing amaximum value and a minimum value for computational results acquired ata lower digit than an input digit; and comparison means for comparing atleast one of the maximum value and the minimum value computed by thecomputing means with data of another digit.
 11. The semiconductorcircuit for arithmetic processing of claim 1 provided with switchingmeans for switching a computing function for input digit data bysupplying a control instruction to the computing unit.
 12. Thesemiconductor circuit for arithmetic processing of claim 1, wherein thecomputing unit is formed using neuron MOS transistors.
 13. Thesemiconductor circuit for arithmetic processing of claim 1, furthercomprising, in order to convert analog data to digital data by narrowingthe comparison range of the analog data; conversion means for convertingthe analog data sequentially every computation time unit from an upperorder digit side of the digital data; and the computing unit or thecomputing circuit for computing output of the conversion means everycomputation time unit from an upper order digit.
 14. An arithmeticprocessing method receiving input of at least one numerical data itemcomprised of a plurality of digits, one digit being input sequentiallyper computing time unit from an upper order digit of the numerical data,comprising: a first process of computing data of an input digit incomputing time units and outputting a computation result obtained bycomputation; a second process of generating a carry as a result of thecomputation of the first process and outputting carry data representingthis carry; and a third process of delaying the computational result bya single computing time unit.
 15. The arithmetic processing method ofclaim 12, wherein from the first process to the third process issequentially repeated.
 16. The arithmetic processing method of claim 15,further comprising: a fourth process of sequentially judging computationresults of the first process from an upper order digit, and a fifthprocess of suspending computation of lower order digits at a point intime where a judgement result of the fourth process is defined.